An ongoing trend in the design of modern electronics equipment is the drive to increase the power efficiency of the devices. Particularly with mobile devices or other battery-powered devices, greater power efficiency is almost a universally desirable attribute. To that end, various types of power saving mechanisms are often employed. For example, considerable emphasis may be placed on managing power states associated with the operation of various functional components or modules of the device. However, the power consumed by an interface used to couple such components may also represent an area where efficiencies may be realized.
In one aspect, many electronic devices employ an interface to provide interconnections between a host processor, memory, and one or more functional elements. As such, power efficiency may be increased when the interface offers one or more power saving modes. In most instances, operating one or more aspects of an electronic device in a reduced power mode comes at the expense of reduction in functionality. When returning to normal operation, a period of time is required for reactivation. This latency is typically proportional to the reduction in power consumed. For example, a power saving mode involving clock gating may have a wake up time on the order of tens of nanoseconds and result in a modest reduction in power. As another example, a power saving mode that deactivates phase locked loop (PLL) circuits may represent a greater power saving but require a wake up time on the order to tens of microseconds. Accordingly, it would be desirable to increase the amount of time the interface operates in a power saving mode without incurring a corresponding reduction in performance of the electronic device. This disclosure satisfies this and other goals.